Please use this identifier to cite or link to this item: https://idr.l3.nitk.ac.in/jspui/handle/123456789/16140
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dc.contributor.authorBhowmik B.
dc.date.accessioned2021-05-05T10:29:51Z-
dc.date.available2021-05-05T10:29:51Z-
dc.date.issued2021
dc.identifier.citationIEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. , , p. -en_US
dc.identifier.urihttps://doi.org/10.1109/TVLSI.2021.3059662
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/16140-
dc.description.abstractNetwork-on-chip (NoC) has emerged as a scalable on-chip communication platform and, hence, has become more popular. However, as the sole communication medium, a single point of failure raised by any permanent fault can cause the failure of the entire system. Subsequently, the NoC has become a critically exposed unit that must be protected. This article primarily presents a test-time-independent and optimally distributed test scheme named ``Dugdugi'' that addresses channel faults, e.g., short in an Octagon and similar NoC architectures to achieve high reliability. The proposed scheme is extended to cover other channel faults, such as stuck-at and transient faults, to give its impression of a comprehensive approach. Experimental results show that the proposed scheme incurs little hardware area and detects all modeled short faults by a few clocks with achieving fault coverage metric up to 100%. Online evaluation reveals the effect of channel-short faults on various network performance metrics. In comparison to prior methodologies, the proposed scheme improves hardware area overhead up to 71.79% and reduces test time over 94.20%. Furthermore, performance overhead, such as packet latency and energy consumption, reduces up to 40.85% and 43.87%, respectively. IEEEen_US
dc.titleDugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networksen_US
dc.typeArticleen_US
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