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DC Field | Value | Language |
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dc.contributor.author | Somayaji, B.J. | |
dc.contributor.author | Bhat, M.S. | |
dc.date.accessioned | 2020-03-30T09:46:14Z | - |
dc.date.available | 2020-03-30T09:46:14Z | - |
dc.date.issued | 2017 | |
dc.identifier.citation | Journal of Low Power Electronics, 2017, Vol.13, 4, pp.669-677 | en_US |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/6846 | - |
dc.description.abstract | This paper presents the design of RESURF based non-conventionalDrain ExtendedMOS (DEMOS) and its parametric analysis. The work investigates the impact of three primary parameters relating to p-implant, namely implant placement distance, implant doping and implant thickness, on device performance and premature avalanche breakdown. To avoid undesirable implant-drain punch-through, a boundary of limits is proposed near drain. Further, the implant parameters are optimized to maximize the ratio of Breakdown Voltage (BVt) to ON-resistance (RON). A breakdown voltage of 21 V at a low RON of 2.5 k? was achieved for a device gate length of 250 nm and gate oxide thickness of 5 nm. Using the optimized device design, the RF/Analog performance parameters are extracted and evaluated to enhance the suitability of the device for high voltage I/O applications in Sub-micron RF-SoC. Copyright � 2017 American Scientific Publishers All rights reserved Printed in the United States of America. | en_US |
dc.title | Triple reduced surface field drain extended MOS device design and its RF performance evaluation for sub-micron RF SoC platform | en_US |
dc.type | Book chapter | en_US |
Appears in Collections: | 2. Conference Papers |
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