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DC Field | Value | Language |
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dc.contributor.author | Hegde, K.V. | - |
dc.contributor.author | Kulkarni, V. | - |
dc.contributor.author | Harshavardhan, R. | - |
dc.contributor.author | Sumam, David S. | - |
dc.date.accessioned | 2020-03-30T09:58:38Z | - |
dc.date.available | 2020-03-30T09:58:38Z | - |
dc.date.issued | 2015 | - |
dc.identifier.citation | Proceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015, 2015, Vol., , pp.196-201 | en_US |
dc.identifier.uri | https://idr.nitk.ac.in/jspui/handle/123456789/7205 | - |
dc.description.abstract | In this paper, we propose an adaptive reconfigurable architecture for image denoising. First part of this paper outlines an efficient noise detection hardware for Gaussian & impulse noise detection and suitable filters for denoising. With a robust noise detection method including a novel Gaussian noise detection method, we also explore the dynamic detection of noise in an image giving adaptability to the architecture for a better quality of denoising. Proposed architecture includes a decision making unit to find out the presence of noise as well as type of the noise, based on which a suitable filter is employed during run-time. An onboard microprocessor controls the reconfiguration and dataflow. Proposed architecture is tested on Xilinx Virtex-6 FPGA with localized noise and mixed noise conditions and it gives superior performance compared to the standard filters used. High quality denoising is achieved with simple filters on a reconfigurable region utilizing smaller area and lesser hardware resources. � 2015 IEEE. | en_US |
dc.title | Adaptive Reconfigurable Architecture for Image Denoising | en_US |
dc.type | Book chapter | en_US |
Appears in Collections: | 2. Conference Papers |
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