Please use this identifier to cite or link to this item: https://idr.l3.nitk.ac.in/jspui/handle/123456789/9909
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dc.contributor.authorSathik
dc.contributor.authorMJ;, Bhatnagar
dc.contributor.authorK;, Sandeep
dc.contributor.authorN;, Blaabjerg
dc.contributor.authorF
dc.date.accessioned2020-03-31T06:51:42Z-
dc.date.available2020-03-31T06:51:42Z-
dc.date.issued2020
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, Vol.67, 1, pp.127-131en_US
dc.identifier.uri10.1109/TCSII.2019.2902908
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/9909-
dc.description.abstractIn this brief, a seven-level (7L) improved packed U-cell (IPUC) inverter with reduced power electronic components is proposed. The presented IPUC inverter has low voltage stress on switches and is capable of voltage boosting. A new voltage balancing method based on logic form equations is developed for regulating the inherent floating capacitor voltage to half the input dc voltage. The proposed 7L IPUC is compared with other state-of-the-art 7L inverters in terms of number of IGBTs, blocking voltage, and driver circuits for attesting its superior merits. The performance of the proposed voltage balancing is verified through a laboratory prototyped 7L IPUC inverter considering varying load conditions and the corresponding results are elucidated.en_US
dc.titleAn Improved Seven-Level PUC Inverter Topology With Voltage Boostingen_US
dc.typeArticleen_US
Appears in Collections:1. Journal Articles

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