Please use this identifier to cite or link to this item: https://idr.l3.nitk.ac.in/jspui/handle/123456789/11962
Title: High-speed and parallel approach for decoding of binary BCH codes with application to Flash memory devices
Authors: Kumar, H.P.
Shripathi, Acharya U.
Shetty, K.R.
Issue Date: 2012
Citation: International Journal of Electronics, 2012, Vol.99, 5, pp.683-693
Abstract: In this article, we propose a high-speed decoding algorithm for binary BCH codes that can correct up to 7bits in error. Evaluation of the error-locator polynomial is the most complicated and time-consuming step in the decoding of a BCH code. We have derived equations for specifying the coefficients of the error-locator polynomial, which can form the basis for the development of a parallel architecture for the decoder. This approach has the advantage that all the coefficients of the error locator polynomial are computed in parallel (in one step). The roots of error-locator polynomial can be obtained by Chien's search and inverting these roots gives the error locations. This algorithm can be employed in any application where high-speed decoding of data encoded by a binary BCH code is required. One important application is in Flash memories where data integrity is preserved using a long, high-rate binary BCH code. We have synthesized generator polynomials for binary BCH codes (error-correcting capability, s) that can be employed in Flash memory devices to improve the integrity of information storage. The proposed decoding algorithm can be used as an efficient, high-speed decoder in this important application. 2012 Taylor & Francis.
URI: https://idr.nitk.ac.in/jspui/handle/123456789/11962
Appears in Collections:1. Journal Articles

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