Low Power Balun LNAs for Narrow-Band and UWB Applications

Abstract

This research work concentrates on the Design and Implementation of single to di erential (balun) Low Noise Ampli ers (LNAs) for narrow-band and ultra wide band (UWB) applications. The transceiver of wireless devices dominate the overall power consumption. Hence, low power designs are to be investigated for enhancement of the battery life. Improving the power e ciency of the front-end will dramatically increases the receiver performance. Furthermore many wireless receivers have indispensable passive/active balun for di erential conversion of incoming single-ended antenna signal. The cynosure of proposed LNAs are low power, single to di erential conversion and diminution of gain and phase error (i.e. less than 1 dB and 10◦ respectively) at the di erential output. A high selectivity, current-reuse balun LNA is proposed for low power wearable and implantable medical devices which are operated in the range of 401 to 406 MHz. An inductive degenerated common source (IDCS) topology has been used for optimum power, noise and impedance matching. The di erential conversion of RF input has been achieved by stacking cascaded stage (stage-II) on top of the IDCS stage (stage-I). In addition, a second design of balun LNA is proposed for UWB applications in the frequency range of 3.1 to 10.6 GHz. The speci cations of UWB are in contrast with the narrow-band design. The UWB radio technology introduces signi cant advantages for short-range communications systems. This technology requires a wide bandwidth, which allows Gigabit data rates over short distances. An exemplary common gate and common source topology (CG-CS) has been used for di erential conversion of the input signal. A CG-CS stage exploits amalgamation of CG stage (for wide-band impedance matching) and CS to curtail signal imbalance, while simultaneously negating noise and distortion of the input matching transistor. The proposed balun exerts a di erential stage on top of CG-CS stage. The improvement of bandwidth has been accomplished using staggered tuning on CG-CS and di erential stages. An Inductor-less balun LNA is also designed for multi-band applications in the range of 0.2 to 2 GHz. The proposed LNA incorporates noise canvcellation and voltage shunt feedback techniques to achieve minimum noise characteristics and low power consumption respectively. In addition, transconductance scaling has been used to improve the noise performance. In this way, noise gure (NF) of LNA below 3 dB is achieved. An additional capacitor is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power e ciency. This research also concentrates on biasing circuits for LNAs to reduce the performance variations against process, supply voltage and temperature (PVT). A conventional biasing circuit leads to variations in the performance parameters of LNA. This is even worse when core transistor of LNA operates in the sub-threshold region. Compensation bias circuits have been designed to minimize the performance variations in LNA parameters. The proposed balun LNAs are implemented in UMC 0.18-µm CMOS technology. Finally, all the proposed designs are validated by rigorous Monte Carlo simulations.