Complexity Analysis of Hardware Architectures for Intra Prediction unit of High Efficiency Video Coding (HEVC)

Abstract

High efficiency Video Coding (HEVC) is the state-of-the-art video coding technique capable of encoding Ultra High Definition (UHD) videos with better compression efficiency and has better reconstruction quality for the same bitrate as compared to its predecessors. Better compression is possible due to its complex partition and prediction methods. These benefits are at the cost of increased computational complexity, which in turn increases resource consumption and processing time. In this work, we design and implement three different architectures, viz: 1) Fully Sequential Architecture (FSA), 2) Semi-parallel Architecture (SPA) and 3) Fully Parallel Architecture (FPA), for the Intra prediction of HEVC on Field Programmable Gate Arrays (FPGA) and discuss the results. These three configurations are tested for the prediction units of sizes 4×4, 8×8 and 16×16. Results show that FSA uses nearly 70% fewer resources than FPA. Also FSA uses 51.73%, 54.33% and 52.2% less resources than SPA for 4×4, 8×8 and 16×16 block sizes, respectively. Also, the FPA implemented for all three pediction unit (PU) sizes is nearly 22 times and 5 times faster than the FSA and SPA, respectively. © 2020 IEEE.