Please use this identifier to cite or link to this item: https://idr.l3.nitk.ac.in/jspui/handle/123456789/7659
Title: Design of an adaptive and reliable network on chip router architecture using FPGA
Authors: Parane, K.
Prabhu, Prasad, B.M.
Talawar, B.
Issue Date: 2019
Citation: 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, 2019, Vol., , pp.-
Abstract: We propose an adaptive, low cost, reliable and high performance router implemented based on a conventional two stage pipeline. The proposed Adaptive routing operates in adaptive mode as soon as the congestion is detected in network. We employ fault tolerant strategies for different components of routers such as input buffer, route compute unit, virtual channel allocation, switch allocation, and crossbar unit. The proposed router architecture differs from existing reliable routers, our implementation maintains the performance of fault tolerance router under massive network workloads by influencing the features of a crossbar, routing algorithm and router pipeline optimization. Our designed router is highly reliable than current fault receptive routers such as Wang[1], Vicis[2], BulletProof[3], RoCo[4] and Poluri[5]. The average latency is reduced by 0.69% and increased by 2.0% compared to fault tolerant and conventional router. � 2019 IEEE.
URI: http://idr.nitk.ac.in/jspui/handle/123456789/7659
Appears in Collections:2. Conference Papers

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